Noise measurements for LDOs

1.4  Low-Dropout Regulators

As we discussed in section 1.3.1, if we can develop a linear regulator with minimized current consumption in the control circuits, and maintain the difference between the input and output voltages at a very low value, the circuit will be very efficient and will have all the valuable specifications of a linear regulator. Using the approximation in Equation (1.26), if we consider a linear regulator circuit with 5 V input and 3.3 V output, the efficiency will be around 66%. If the input is 3.5 for the same output, the theoretical best efficiency can be close to 94%, which is very much better than the efficiency of com-mon switching regulators. 

Based on the simple concept discussed above, to power modern portable devices such as cell phones, notebooks, and PDAs, a unique category of linear regulator ICs, low-dropout (LDO) regulators, have emerged during the last two decades. These were used in tandem with switching regulators to power noise-sensitive mixed-signal cir-cuits, RF circuit blocks, and other noise-sensitive circuits. LDOs are available in a wide variety of output voltages and current capacities. Many LDOs are tailored to applications where a good response to a fast-step current transient is important. These devices have captured a large share of power management ICs in the early part of this decade [6]. This kind of a power supply solution is very helpful in low voltage rail based where load current can change rapidly, creating very high current slew rates [7].

1.4.1  Basic Concept of an LDO

Figure 1.11 depicts the simplified block diagram of an LDO regulator IC. The main com-ponents are the pass element, precision reference, feedback network, and error ampli-fier. The input and output capacitors are the only key components of an LDO solution that are not contained within the monolithic LDO. Table 1.1 compares different options available for the pass transistor in a linear regulator and the advantages and disad-vantages of the approaches. This is more applicable to modern LDO ICs. In discussing the details and design approaches to LDO-type regulators, let’s start from the simple

Simplified block diagram of an LDO

Simplified concepts in LDO architecture

concept of Figure 1.12(a). If we consider the case of battery input into an LDO where the voltage fluctuates as the load current varies, or as the battery drains the series resistance increases, it can be shown that to keep the output voltage, Vo, constant,

the output voltage

where VB and RS are battery voltage and the resistance due to the LDO series pass ele-ment respectively, while RL represents the load resistance. We can represent the same relationship as

RL represents the load resistance

where VLDO is the voltage across the series pass element. As depicted in Figure 1.12(b), if we have a feedback circuit, the feedback circuit is expected to keep controlling the value of RS when VLDO fluctuates. As shown in Table 1.1, we can use any configuration of transistors as the series element, and in most new commercial LDOs MOS field effectPMOS LDO

transistors are used. Figure 1.12(c) indicates the feedback loop arrangement with an error amplifier, which could be easily implemented by using an op-amp.

The basic PMOS LDO topology shown in Figure 1.13(a) comprises an error amplifier that has the output voltage of VX and gain of AEA. The power transistor can be repre-sented using the small signal equivalent model of transconductance gm and output resis-tance rop as shown in Figure 1.13(b).

According to the above representation in Figure 1.13(b), current I can be written as

current I can be written

Also

Equations

Using Equations (1.33), (1.34), and (1.35),Solving Equations

1.4.2  Important Parameters of LDOs

1.4.2.1  Dropout Voltage

This is the minimum voltage difference allowed for the series pass element before the regulator goes out of regulation. Usually a PMOS transistor-based version allows very low value and hence a high efficiency.

1.4.2.2  Input Voltage Range

This is the range of input voltages where the LDO remains in regulation. Lower value depends on the dropout voltage, while the higher end depends on the process capability, the heat sinking requirements, etc.

1.4.2.3  Regulated Output Voltage Range

This is the range of output voltage when the LDO is in regulation under steady-state con-ditions. However, when the output load current changes fast, transient over- or under-voltage conditions may occur, which will exceed these limits for short durations.

Input output relationships of LDOs

1.4.3  Application and Design Implications

A common application area of LDOs is the portable products where processors are coupled with many mixed-signal circuitries. In these circumstances two important specifications of a DC power supply become very dominant. These are the output noise and the transient response. Many processors frequently go through sleep and wakeup type sequences where the load currents vary suddenly from very low values to near maximum. These transitions in state-of-the-art products could generate current varia-tions with current slew rates in the range of 10 A/µs to over 250 A/µs. Typical LDO

Important Secondary Specifications of LDOs

load transient performance for a chip such as TPS763650 from Texas Instruments is shown in Figure 1.15(a), while steady-state performance is shown in Figure 1.15(b). In Figure 1.15(a), ΔVLDR indicates the steady-state response, which is the same value depicted in Figure 1.15(b), but transient changes can always exceed this value as depicted in Figure 1.15(a). In a well-designed LDO-based power supply, this transient fluctuation needs to be minimized.

 

In order to improve on the transient behavior, there are many improvements incorpo-rated into LDO chips. One such example is the use of a fast transient loop in LDOs such as TPS75433 from Texas Instruments for low and high currents [9].

In the majority of LDOs and quasi-LDOs (where a composite NPN-PNP pair is used as the pass device), the pass device or the driver is a lateral PNP. Even though a PNP is better at providing a lower dropout voltage than an NPN [10], a lateral PNP is a low-frequency cutoff device with a poor transient response. For this reason, proper selection of the external output capacitor is important for the stability of the loop and

Load regulation and transient performance of a typical LDO-TPS76350

Figure 1.15  Load regulation and transient performance of a typical LDO-TPS76350 from Texas Instruments: (a) load transient response; (b) steady-state performance. (Adapted from Lee, B.STexas Instruments, Application Report SLVA072, 1999.)

adequate transient response. The compensation capacitor determines three key charac-teristics of an LDO: startup delay, load transient response, and loop stability. The startup time is approximately given by

The startup

where C is the value of the output capacitor and Ilimit is the current limit of the regulator. If C is fully discharged before the regulator is powered up, the regulator will limit current during startup, and the time to reach the nominal Vo will be delayed. Conversely, if C is too small, the output voltage will overshoot the nominal Vo during startup. Because it is impossible to investigate all three characteristics at once, the designer should concen-trate on first achieving a stable loop design and then check the startup delay and load transient response. In general if a single pole system can be created, and if the crossover frequency is selected to ensure that the system can quickly respond to load transients without undue ringing at the output, the design will be stable. For stability, the phase margin should be more than 45°. Unfortunately, an LDO has three dominant poles, and two are set by the regulator IC and the third is a function of the load and the output capacitor. The first pole, determined by the error amplifier, generally occurs between 10 and 300 Hz; the second pole, due to the pass device (or the PNP bias device of a com-pound regulator), is usually between 100 and 300 kHz. The third pole, set by the load and the output capacitor, occurs within the same range as the error amplifier or even slightly lower at light loads. Figure 1.16(a) shows the simplified case of a load and output capacitor combination.

It can be shown that the pole and the zero created by the load are given by

the pole and the zero

Based on the discussion in chapter 5, section 5.5, where added poles and zeros change the Bode plot, it is apparent that the zero due to capacitor ESR modifies the total response of the circuit. Figure 1.16(b1) shows the case where the output is marginally stable for ESR = 3.0 Ω. As depicted in Figure 3.16(b2), when the ESR is reduced to 1.0 Ω, the sys-tem’s phase margin increases and the system becomes stable. When the ESR is lowered further, the system can become unstable, as in Figure 1.16(b2). The capacitor used at the output should have some stability within the operational temperature ranges. Figure 5.16 shows typical aluminum electrolytic capacitor characteristics over frequency and tem-perature. Based on the discussion related to Figure 1.16, it is important for designers to carefully examine the parameter changes of capacitors over frequency and temperature to achieve a stable design. Details can be found in King [9], O’Malley [11], Simpson [12, 13], and Goodenough [14].

Based on the discussion in chapter 5, section 5.5, where added poles and zeros change the Bode plot, it is apparent that the zero due to capacitor ESR modifies the total response of the circuit. Figure 1.16(b1) shows the case where the output is marginally stable for ESR = 3.0 Ω. As depicted in Figure 3.16(b2), when the ESR is reduced to 1.0 Ω, the sys-tem’s phase margin increases and the system becomes stable. When the ESR is lowered further, the system can become unstable, as in Figure 1.16(b2). The capacitor used at the output should have some stability within the operational temperature ranges. Figure 5.16 shows typical aluminum electrolytic capacitor characteristics over frequency and tem-perature. Based on the discussion related to Figure 1.16, it is important for designers to carefully examine the parameter changes of capacitors over frequency and temperature to achieve a stable design. Details can be found in King [9], O’Malley [11], Simpson [12, 13], and Goodenough [14].

1.4.4  LDO Applications and Development Directions

LDOs have gained popularity with the growth of portable battery-powered devices. Many circuit blocks in the portables such as cellular phones, cameras, and laptops have many noise-sensitive mixed-signal components, which may not tolerate the RFI/EMI 

Effect of the load on stability

Figure 1.16  Effect of the load on stability: (a) simplified load and output capacitor combination; (b1) Bode plot of the output for a practical LDO based on a regulator IC such as CS 8156 from ON Semiconductor for different cases of ESR values: (b1) RO = 120 Ω and C = 22 μF with ESR = 3 Ω; (b2) RO = 120 Ω and C = 22 μF with ESR = 1 Ω; (b3) RO = 120 Ω and C = 22 μ F with ESR = 0.01 Ω. (Courtesy of O’Malley, Application Note SR003AN/D, rev. 1, ON Semiconductor, Phoenix, AZ, 2001.)

issues of switching regulators. In these circumstances, LDOs or tandem combinations of LDO and switch-mode regulator are the only practical solution, provided that the efficiency issue can be managed. In most portable devices, LDOs are widely used as they occupy a very small PCB area and do not use any bulky parts such as inductors and the like. LDOs are particularly attractive in systems with noise-sensitive system-on-chip (SoC) applications where battery power is used. LDOs also find applications in auto-motive environments because of the rapid voltage changes of the 12 V rail during cold

startup [15]. Most LDOs are used in powering high-power processors where load current changes in step mode with high current slew rates. Schiff [16] and Rincon-Mora and Allen [17] provide design guidelines to deal with these conditions. With the initiatives to incorporate more commercial-off-the-shelf (COTS) components into military systems, some companies such as Linear Technology and others have developed high-reliability military plastic (MP) packaged LDOs with reverse voltage protection and current limit-ing over the full range of military operating temperatures [18]. Some devices such as LT3070 from Linear Technology could supply 5 A of load current at digitally program-mable voltages from 0.8 V to 1.8 V with dropout voltages as low as 85 mV are examples of these MP-packaged devices. Details on frequency compensation of LDOs are avail-able in Kwok and Mock [19] and Chava and Silva-Martinez [20]. For applications with extra low LDO voltages, ultra-low- dropout (ULDO) linear regulators based on bipolar CMOS-DMOS (BCD) technologies are available [21].

1.4.5  Low-Noise Application Requirements and Noise Measurements for LDO Output

Some of the LDO regulators are specially designed for low-noise requirements [22] within cellular handsets and other portable applications, because most switch-mode power sup-plies are too noisy for these applications. The noise performance of these components sometimes needs to be quantified, and special measurement setups may be necessary. In this process one should ensure that the LDO meets the system’s noise requirement within the entire bandwidth of interest, typically in the range of 10 Hz to 100 kHz. Figure 1.17 indicates a suitable filter structure for testing the noise performance of LDOs in this frequency band. In LDO noise measurement, special consideration should be given to ground loop elimination; hence, all power supplies should be battery based, and thermally responding RMS meters should be used for measurements [23]. General performance verification of LDOs is discussed in Williams and Owen [24].

1.4.6  Adjustable Output LDO Circuits

For applications where nonstandard voltages are required, an adjustable LDO is a good choice, but getting the highest accuracy from such an IC may require a few circuit tricks. Figure 1.18 shows a few examples, including the use of an adjustable reference for improving accuracy [25]. For applications with hot-swap requirements, LDO ICs can be used with special current limiting arrangements [26].

Noise measurements for LDOs

Noise measurements for LDOs

Adjustable LDO circuits

1.4.7  Battery-Powered Applications and PMOS-Based LDOs

For battery-powered applications, PMOS-based LDOs provide acceptable solutions. The factors to be considered include dropout voltage, ground current, noise, input voltage, and thermal response. Typical ground current components in an LDO are shown in Figure 1.19(a). Figures 1.19(b) and 1.19(c) show the comparative performance of typical PNP LDOs and PMOS-based LDOs. For details, see Christ [27]. Given the demand from many portable battery-powered applications, there is a considerable research effort on LDOs continuing at universities, and some of these are reflected in References [28–32]. References [33] and [34] provide practical design guidelines for end users, including some thermal design aspects [34].

Another serious possibility is to have very high end-to-end efficiency-based superca-pacitor enhancements to LDO-based linear regulator systems [35–37].

Ground currents in an LDO and comparison of PNP and PMOS types

 

 

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